july 2008 dsc-5326/02 1 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. ? features 64k x 16 advanced high-speed cmos static ram equal access and cycle times ? commercial: 10/12/15/20ns ? industrial: 12/15/20ns one chip select plus one output enable pin bidirectional data inputs and outputs directly lvttl-compatible low power consumption via chip deselect upper and lower byte enable pins single 2.5v power supply available in 44-pin plastic soj, 44-pin tsop, and 48-ball plastic fbga packages description the idt71t016 is a 1,048,576-bit high-speed static ram organized as 64k x 16. it is fabricated using idt?s high-performance, high-reliability cmos technology. this state-of-the-art technology, combined with inno- vative circuit design techniques, provides a cost-effective solution for high- speed memory needs. the idt71t016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. all bidirectional inputs and outputs of the idt71t016 are lvttl-compatible and operation is from a single 2.5v supply. fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. the idt71t016 is packaged in a jedec standard a 44-pin plastic soj, 44-pin tsop type ii, and a 48-ball plastic 7 x 7 mm fbga. functional block diagram 2.5v cmos static ram 1 meg (64k x 16-bit) idt71t016sa
6.42 2 idt71t016sa, 2.5v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges 123456 a ble oe a 0 a 1 a 2 nc bi/o 8 bhe a 3 a 4 cs i/o 0 ci/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 dv ss i/o 11 nc a 7 i/o 3 v dd ev dd i/o 12 nc nc i/o 4 v ss fi/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 gi/o 15 nc a 12 a 13 we i/o 7 hnc a 8 a 9 a 10 a 11 nc 5326 tbl 02a pin configurations tsop top view pin description truth table (1) note: 1. h = v ih , l = v il , x = don't care. a 0 ? a 15 address inputs input cs chip select input we write enable input oe output enable input bhe high byte enable input ble low byte enable input i/o 0 ? i/o 15 data input/output i/o v dd 2.5v power power v ss ground gnd 5326 tbl 01 cs oe we ble bhe i/o 0 -i/o 7 i/o 8 -i/o 15 function h x x x x high-z high-z deselected ? standby llh l h data out high-z low byte read l l h h l high-z data out high byte read llh l l data out data out word read lxl l l data in data in word write lxl l h data in high-z low byte write lxl h l high-z data in high byte write l h h x x high-z high-z outputs disabled l x x h h high-z high-z outputs disabled 5326 tbl 02 fbga (bf48-1) top view
6.42 3 idt71t016sa, 2.5v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges parameter 71t016sa10 71t016sa12 71t016sa15 71t016sa20 symbol com'l com'l ind com'l ind com'l ind unit i cc dynamic operating current cs < v lc , outputs open, v dd = max., f = f max (3) max. 160 150 160 130 130 120 120 ma typ. (4) 90 85 ____ 80 ____ 80 ____ i sb dynamic standby power supply current cs > v hc , outputs open, v dd = max., f = f max (3) 45 40 45 35 35 30 30 ma i sb 1 full standby power supply current (static) cs > v hc , outputs open, v dd = max., f = 0 (3) 10 15 15 15 15 15 15 ma 5326 tbl 8 absolute maximum ratings (1) recommended operating temperature and supply voltage dc electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) capacitance (t a = +25c, f = 1.0mhz) recommended dc operating conditions dc electrical characteristics (1,2) (v dd = min. to max., v lc = 0.2v, v hc = v dd ? 0.2v) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. this parameter is guaranteed by device characterization, but not production tested. notes: 1. all values are maximum guaranteed values. 2. all inputs switch between 0.2v (low) and v dd ? 0.2v (high). 3. f max = 1/t rc (all address inputs are cycling at f max ); f = 0 means no address input lines are changing . 4. typical values are measured at 2.5v, 25c and with equal read and write cycles. this parameter is guaranteed by device charac terization but is not production tested. symbol rating value unit v dd supply voltage relative to v ss ?0.3 to +3.6 v v in , v out terminal voltage relative to v ss ?0.3 to v dd +0.3 v t bias temperature under bias ?55 to +125 o c t stg storage temperature ?55 to +125 o c p t power dissipation 1.25 w i out dc output current 50 ma 5326 tbl 03 grade temperature v ss v dd commercial 0c to +70c 0v see below industrial -40c to +85c 0v see below 5326 tbl 04 symbol parameter min. typ. max. unit v dd supply voltage 2.375 2.5 2.625 v vss ground 0 0 0 v v ih input high voltage 1.7 ____ v dd +0.3 (1) v v il input low voltage ?0.3 (2) ____ 0.7 v 5326 tbl 05 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 6 pf c i/o i/o capacitance v out = 3dv 7 pf 5326 tbl 06 symbol parameter test condition idt71t016sa unit min. max. |i li | input leakage current v dd = max., v in = v ss to v dd ___ 5a |i lo | output leakage current v dd = max., cs = v ih , v out = v ss to v dd ___ 5a v ol output low voltage i ol = 2.0ma, v dd = min. ___ 0.7 v v oh output high voltage i oh = 2.0ma, v dd = min. 1.7 ___ v 5326 tbl 07 notes: 1. v ih (max) = v dd + 1.0v a.c. (pulse width less than t cyc /2) for i < 20 ma, once per cycle. 2. v il (min) = -1.0v a.c. (pulse width less than t cyc /2) for i < 20 ma, once per cycle.
6.42 4 idt71t016sa, 2.5v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges ac test conditions ac test loads figure 3. output capacitive derating figure 1. ac test load figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow, and t whz ) *including jig and scope capacitance. input pulse levels inp ut rise /fall time s inp ut timing re fe re nce le ve ls output reference levels ac test load 0v to 2.5v 1.5ns (v dd /2) (v dd /2) see figure 1, 2 and 3 5326 tbl 09 +1.25v 50 ? i/o z 0 =50 ? 5326 drw 0 3 30pf
6.42 5 idt71t016sa, 2.5v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges 71t016sa10 (2) 71t016sa12 71t016sa15 71t016sa20 symbol parameter min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 10 ____ 12 ____ 15 ____ 20 ____ ns t aa address access time ____ 10 ____ 12 ____ 15 ____ 20 ns t acs chip select access time ____ 10 ____ 12 ____ 15 ____ 20 ns t cl z (1 ) chip select lo w to output in low-z 4 ____ 4 ____ 5 ____ 5 ____ ns t chz (1 ) chip select hig h to output in high-z ____ 5 ____ 6 ____ 6 ____ 8ns t oe output enable low to output valid ____ 5 ____ 6 ____ 7 ____ 8ns t ol z (1) output enable lo w to output in low-z 0 ____ 0 ____ 0 ____ 0 ____ ns t ohz (1 ) output enable hig h to output in high-z ____ 5 ____ 6 ____ 6 ____ 8ns t oh output hold from address change 4 ? 4 ? 4 ? 4 ? ns t be byte enable low to output valid ? 5 ? 6 ? 7 ____ 8ns t bl z (1 ) byte enable lo w to output in low-z 0 ____ 0 ____ 0 ____ 0 ____ ns t bhz (1 ) byte enable hig h to output in high-z ____ 5 ____ 6 ____ 6 ____ 8ns write cycle t wc write cycle time 10 ____ 12 ____ 15 ____ 20 ____ ns t aw address valid to end of write 7 ____ 8 ____ 10 ____ 12 ____ ns t cw chip select low to end of write 7 ____ 8 ____ 10 ____ 12 ____ ns t bw byte enable low to end of write 7 ____ 8 ____ 10 ____ 12 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wr address hold from end of write 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 7 ____ 8 ____ 10 ____ 12 ____ ns t dw data valid to end of write 5 ____ 6 ____ 7 ____ 9 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ 0 ____ ns t ow (1 ) write enable high to output in low-z 3 ____ 3 ____ 3 ____ 3 ____ ns t whz (1 ) write enable lo w to output in high-z ____ 5 ____ 6 ____ 6 ____ 8ns 5326 tb l 10 timing waveform of read cycle no. 1 (1,2,3) notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. oe , bhe , and ble are low. ac electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) notes: 1. this parameter is guaranteed with the ac load (figure 2) by device characterization, but is not production tested. 2. 0 0 c to +70 0 c temperature range only.
6.42 6 idt71t016sa, 2.5v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges timing waveform of read cycle no. 2 (1) notes: 1. a write occurs during the overlap of a low cs , low bhe or ble , and a low we . 2. oe is continuously high. if during a we controlled write cycle oe is low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low or bhe and ble low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4) notes: 1. we is high for read cycle. 2. address must be valid prior to or coincident with the later of cs , bhe , or ble transition low; otherwise t aa is the limiting parameter. 3. transition is measured 200mv from steady state.
6.42 7 idt71t016sa, 2.5v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges timing waveform of write cycle no. 2 ( cs controlled timing) (1,4) notes: 1. a write occurs during the overlap of a low cs , low bhe or ble , and a low we . 2. oe is continuously high. if during a we controlled write cycle oe is low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low or bhe and ble low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. timing waveform of write cycle no. 3 ( bhe , ble controlled timing) (1,4)
6.42 8 idt71t016sa, 2.5v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges ordering information
the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 9 idt71t016sa, 2.5v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com rev date page description 0 08/23/01 created new datasheet 1 04/16/04 p. 1-8 updated datasheet to full release version. p. 3 updated overshoot and undershoot specifications and typical dc electrical characteristics. 2 07/14/08 p. 1,2,6,7 corrected pin labels output enable, chip select, write enable, high and low byte enables to be oe , cs , we , bhe , ble to reflect active low nature.
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